DocumentCode
3236575
Title
Genetic algorithm based test scheduling and test access mechanism design for system-on-chips
Author
Chattopadhyay, Santanu ; Reddy, K. Sudarsana
Author_Institution
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., India
fYear
2003
fDate
4-8 Jan. 2003
Firstpage
341
Lastpage
346
Abstract
We present a genetic algorithm (GA) based approach to solve the problems of test scheduling and test access mechanism partition for system on chips. The approach provides highly optimal results, comparable to the integer linear programming formulation of similar problems within very small CPU times. The results of GA based approach are shown to be superior to the heuristic approaches proposed in the literature.
Keywords
automatic testing; genetic algorithms; integrated circuit testing; scheduling; system-on-chip; CPU times; genetic algorithm; heuristic approaches; system-on-chips; test access mechanism; test scheduling; Algorithm design and analysis; Circuit testing; Design for testability; Genetic algorithms; Job shop scheduling; Logic testing; Parallel processing; Processor scheduling; System testing; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2003. Proceedings. 16th International Conference on
ISSN
1063-9667
Print_ISBN
0-7695-1868-0
Type
conf
DOI
10.1109/ICVD.2003.1183160
Filename
1183160
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