Title :
Interface design techniques for single-chip systems
Author :
Bell, Robert H. ; John, Lizy Kurian
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
Quantifies the performance of typical functional unit interface designs in single-chip systems. We introduce a specific equation to guide the design of optimal module interfaces. We show how the equation and interface considerations lead to more efficient queue structures for request buffering. For a specific single-chip design, we use simulation to show that: 1) For low request rates, queue structure is relatively unimportant to either system request bandwidth or service latency; 2) For a narrow range of request rates, queue structure has a significant impact on system latency but not bandwidth; 3) For high request rates, queue structure impacts bandwidth significantly; 4) As request service latencies increase relative to the queue size, the impact of the queue structure decreases; 5) Given a particular range of request rates, the complexity of particular queue structures can be traded off with the desired system bandwidth and latency performance. For a particular single-chip system, a maximum 29% bandwidth improvement and 60% latency improvement are achieved when using the more efficient queue structures.
Keywords :
buffer circuits; circuit CAD; circuit optimisation; integrated circuit design; logic CAD; system-on-chip; functional unit interface designs; optimal module interfaces; queue structures; request buffering; request rates; semi-custom electronics; service latency; single-chip systems; system request bandwidth; Bandwidth; Hardware; Interference constraints; Performance analysis; Process design; Queueing analysis; Steady-state; Traffic control; Very large scale integration; Wiring;
Conference_Titel :
VLSI Design, 2003. Proceedings. 16th International Conference on
Print_ISBN :
0-7695-1868-0
DOI :
10.1109/ICVD.2003.1183167