Device integration of a 0.35 μm CMOS on shallow SIMOX technology for high-speed and low-power applications

Author

Adan, A.O. ; Naka, T. ; Kaneko, S. ; Urabe, D. ; Higashi, K. ; Kagisawa, A.

Author_Institution

VLSI Dev. Lab., Sharp Corp., Nara, Japan

fYear

1996

fDate

30 Sep-3 Oct 1996

Firstpage

116

Lastpage

117

Abstract

Summary form only given. SOI based devices bring the potential of very low voltage operation at high speed as required in portable electronic systems. However, to realize the advantages of SOI MOSFETs in a commercial product (1) high-performance transistors, with (2) reproducible and good controllability need to be realized. Furthermore, (3) reliability against the environment (e.g. ESD) must be demonstrated. In this work, a high performance 0.35 μm CMOS process implemented on ultra-thin (shallow) SIMOX wafers is presented. This process is aimed at low-power, low-voltage (Vdd=l to 1.8 V) and high speed application for portable communication devices. The main considerations in the process/device design and integration are discussed and manufacturability demonstrated

Keywords

CMOS integrated circuits; SIMOX; integrated circuit manufacture; integrated circuit technology; 0.35 micron; 1 to 1.8 V; SOI MOSFETs; SOI based devices; Si; controllability; high performance CMOS process; high-speed applications; low voltage operation; low-power applications; manufacturability; portable communication devices; reliability; shallow SIMOX technology; ultra-thin wafers; Biological system modeling; Dielectrics; Doping profiles; Electron devices; Electrostatic discharge; Humans; Integrated circuit interconnections; Power dissipation; Reliability engineering; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 1996. Proceedings., 1996 IEEE International

Conference_Location

Sanibel Island, FL

ISSN

1078-621X

Print_ISBN

0-7803-3315-2

Type

conf

DOI

10.1109/SOI.1996.552521

Filename

552521