DocumentCode
3237167
Title
A scalable SOI technology for three successive generations: 0.18, 0.13 and 0.1 μm for low-voltage and low-power applications
Author
Pelloie, J.L. ; Faynot, O. ; Raynaud, C. ; Dunne, B. ; Martin, F. ; Tedesco, S. ; Hartmann, J.
Author_Institution
LETI, CEA-Technol. Avancees, Grenoble, France
fYear
1996
fDate
30 Sep-3 Oct 1996
Firstpage
118
Lastpage
119
Abstract
Optimized 0.18 μm gate length NMOSFET and PMOSFET SOI devices have been demonstrated with high electrical performances for low-voltage and low-power applications. The electrical results show that this SOI design can be easily scaled down for the next generations and no heavy ion implant (In or Sb) is required
Keywords
MOSFET; silicon-on-insulator; 0.1 micron; 0.13 micron; 0.18 micron; NMOSFET; PMOSFET; electrical performance; low-power applications; low-voltage applications; scalable SOI technology; Aging; Annealing; Current measurement; Hot carriers; Length measurement; Low voltage; MOS devices; MOSFET circuits; Threshold voltage; Transconductance;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 1996. Proceedings., 1996 IEEE International
Conference_Location
Sanibel Island, FL
ISSN
1078-621X
Print_ISBN
0-7803-3315-2
Type
conf
DOI
10.1109/SOI.1996.552522
Filename
552522
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