Genetic algorithm based approach for low power combinational circuit testing

Author

Chattopadhyay, Santanu ; Choudhary, Naveen

Author_Institution

Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., India

fYear

2003

fDate

4-8 Jan. 2003

Firstpage

552

Lastpage

557

Abstract

With the advancement in automation, periodic testing of electronic circuits during their lifetime is becoming more and more important. For such a circuit, it is thus very much necessary to reduce the power requirement during the testing,phase also. This paper presents a genetic algorithm based formulation to solve the problem of generating a test pattern set such that it has high fault coverage and low power consumption. Exhaustive experimentation done on ISCAS85 combinational benchmark suite has shown that the this tool results in up to 78% reduction in transition activity over the original test set generated by ATPGs like ATALANTA.

Keywords

automatic test pattern generation; combinational circuits; fault diagnosis; genetic algorithms; integrated circuit testing; logic testing; low-power electronics; ATALANTA; ATPGs; ISCAS85 combinational benchmark suite; fault coverage; genetic algorithm; low power combinational circuit testing; periodic testing; power requirement; test pattern set; transition activity; Automatic testing; Automation; Circuit testing; Combinational circuits; Electronic circuits; Electronic equipment testing; Genetic algorithms; Life testing; Power generation; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2003. Proceedings. 16th International Conference on

ISSN

1063-9667

Print_ISBN

0-7695-1868-0

Type

conf

DOI

10.1109/ICVD.2003.1183192

Filename

1183192