DocumentCode
3237262
Title
A run-time reconfiguration algorithm for VLSI arrays
Author
Jigang, Wu ; Thambipillai, Srikanthan
Author_Institution
Centre for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore, Singapore
fYear
2003
fDate
4-8 Jan. 2003
Firstpage
567
Lastpage
572
Abstract
This paper discusses the NP-complete problem of reconfiguring a two-dimensional degradable VLSI/WSI array under the row and column routing constraints. A new strategy for row selection in the logical array is proposed and the earlier approach by Low et. al. is simplified. A flaw in Low´s algorithm is also addressed. Experimental results show that our algorithm is approximately 50% faster than the most efficient algorithm, cited in the literature, without loss of performance.
Keywords
VLSI; circuit CAD; computational complexity; high-speed integrated circuits; microprocessor chips; network routing; reconfigurable architectures; wafer-scale integration; Low´s algorithm; NP-complete problem; VLSI arrays; fault-tolerance; logical array; routing constraints; row selection; run-time reconfiguration algorithm; two-dimensional degradable VLSI/WSI array; Degradation; Embedded system; Fault tolerance; Logic arrays; NP-complete problem; Redundancy; Routing; Runtime; Switches; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2003. Proceedings. 16th International Conference on
ISSN
1063-9667
Print_ISBN
0-7695-1868-0
Type
conf
DOI
10.1109/ICVD.2003.1183194
Filename
1183194
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