Footprint design optimization in SiGe BiCMOS SOI technology

Author

Chen, Tianbing ; Babcock, Jeff ; Nguyen, Yen ; Greig, Wendy ; Lavrovskaya, Natasha ; Thibeault, Todd ; Ruby, Scott ; Adler, Steve ; Krakowski, Tracey ; Kim, Jonggook ; Sadovnikov, Alexei

Author_Institution

Adv. Process Technol. Dev., Nat. Semicond. Corp., Santa Clara, CA

fYear

2008

fDate

13-15 Oct. 2008

Firstpage

208

Lastpage

211

Abstract

Footprint design in SiGe BiCMOS SOI technology is described in this paper to improve device performance matrix. The safe operating area (SOA) for a SiGe hetero-junction bipolar transistor (HBT) fabricated on silicon on insulator (SOI) is significantly improved as the footprint area increases. The Early voltage for SiGe HBT on SOI at medium-high bias range also increases substantially with footprint area increase. Peak f_T and noise figure improves slightly with footprint, and peak f_MAX improves slightly then decreases significantly at very large footprint area. A generic tube-area-limited thermal resistance model for BiCMOS devices on SOI is also proposed.

Keywords

BiCMOS integrated circuits; Ge-Si alloys; optimisation; semiconductor device models; semiconductor materials; silicon-on-insulator; thermal conductivity; BiCMOS SOI technology; SiGe; footprint design optimization; noise figure; safe operating area; silicon on insulator; thermal resistance model; BiCMOS integrated circuits; Bipolar transistors; Design optimization; Germanium silicon alloys; Heterojunction bipolar transistors; Semiconductor optical amplifiers; Silicon germanium; Silicon on insulator technology; Thermal resistance; Voltage; SiGe HBT; footprint; impact ionization; safe operating area; self heating; thermal resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting, 2008. BCTM 2008. IEEE

Conference_Location

Monteray, CA

ISSN

1088-9299

Print_ISBN

978-1-4244-2725-3

Electronic_ISBN

1088-9299

Type

conf

DOI

10.1109/BIPOL.2008.4662745

Filename

4662745