Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures

Author

Coste, Nicolas ; Garavel, Hubert ; Hermanns, Holger ; Hersemeule, Richard ; Thonnart, Yvain ; Zidouni, Meriem

Author_Institution

STMicroelectronics, Grenoble

fYear

2008

fDate

10-14 March 2008

Firstpage

88

Lastpage

89

Abstract

As levels of parallelism are becoming increasingly complex in multiprocessor architectures GALS and asynchronous circuits, methodologies and software tools are needed to verify their functional behavior (qualitative properties) and to predict their performance (quantitative properties). This paper presents the work currently done in the multival project (pole de competitivite mondial Minalogic), in which verification and performance evaluation tools developed at INRIA and Saarland University are applied to three industrial architectures designed by Bull CEA/Leti and STMicroelectronics.

Keywords

circuit analysis computing; embedded systems; multiprocessing systems; performance evaluation; GALS; asynchronous circuits; electronic engineering computing; embedded system design; multiprocessor multithreaded architectures; multival project; performance evaluation; pole de competitivite mondial Minalogic; Computer architecture; Delay; Embedded system; Hardware; Network-on-a-chip; Parallel processing; Software tools; Streaming media; Telecommunications; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 2008. DATE '08

Conference_Location

Munich

Print_ISBN

978-3-9810801-3-1

Electronic_ISBN

978-3-9810801-4-8

Type

conf

DOI

10.1109/DATE.2008.4484666

Filename

4484666