Performance prediction on graphics hardware using software simulation

We describe our work in using software simulation to provide useful chip level performance metrics for our future graphics chips. Because of the deep pipeline and the deep FIFOs, most of the blocks in the graphics chip are expected to be busy most of the time. For this reason, we dropped event-driven simulation and chose a cycle-based approach. We designed an efficient scheduler along with other computation reduction methods to facilitate cycle-based simulation in a multiple clock frequencies setting. The resulting platform allows us to use realistic workload captured from real applications. We are able to see bottlenecks as well as throughput at each stage and to make performance/area tradeoffs based on how they impact performance