The architecture of high-speed matched filter for searching synchronization in DSSS receiver

Author

Song, Myong-Lyol

Volume

2

fYear

2002

fDate

25-28 Nov. 2002

Firstpage

878

Abstract

A high-speed matched filter for searching synchronization in direct sequence spread spectrum (DSSS) receiver is studied. A model to implement the matched filter by hardware description languages (HDL) is proposed. The proposed model is based on parallel processing and pipeline architecture including circular buffer, multiplier, adder, and code look-up table. The proposed model is analyzed with respect to the performance and compared with a conventional digital signal processor (DSP) implementation.

Keywords

hardware description languages; matched filters; parallel architectures; pipeline processing; radio receivers; spread spectrum communication; synchronisation; DSP implementation; DSSS receiver; FPGA; HDL; adder; circular buffer; code look-up table; digital signal processor; direct sequence spread spectrum; hardware description languages; held programmable gate array; high-speed matched filter architecture; multiplier; parallel processing; pipeline architecture; searching synchronization; Adders; Digital signal processors; Hardware design languages; Matched filters; Parallel processing; Performance analysis; Pipelines; Signal analysis; Spread spectrum communication; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Communication Systems, 2002. ICCS 2002. The 8th International Conference on

Print_ISBN

0-7803-7510-6

Type

conf

DOI

10.1109/ICCS.2002.1183257

Filename

1183257