Successful modeling of a semiconductor R&D facility

A chief limitation on process development cycle time is the time it takes to process wafers. Hewlett Packard Co. has shortened this time by using discrete-event simulation of its R&D fabrication facility to better understand its capacity limitations and to analyze how changes affect the cycle times of complete wafer processing. Results include Pareto charts of equipment according to the impacts that changes in their mean-time-between-failure (MTBF) and/or mean-time-to-repair (MTTR) parameters have on wafer cycle times. Results also include a Pareto chart of operator skills and their impact on cycle times; that is, one can know how much effect there is on cycle times when staffing is changed to satisfy needs for a specific operator skill. Similarly, it is possible to evaluate effects of shift schedules and end-of-shift wafer processing decisions. Furthermore, simulation reveals the relative benefits of applying different dispatching rules (such as first in, first out, shortest-processing time, least-work-in-next queue, etc.) and of different inventory-level control policies