Design and implementation of a parity-based BIST scheme for FPGA global interconnects

Author

Sun, Xiaoling ; Xu, Jian ; Jian Xu ; Trouborst, Pieter

Author_Institution

Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada

Volume

2

fYear

2001

fDate

2001

Firstpage

1251

Abstract

This paper presents the design and implementation of a parity-based built-in self-test (BIST) scheme for interconnects of field programmable gate arrays (FPGAs). The self-test is achieved by using a set of proposed test configurations (TCs). Design flows were developed to enable the implementation. We utilized the existing features of FPGA design tools and developed a tool to automate the required interconnect routing. The conventional FPGA design flow was used to implement the BIST circuitry. A complete FPGA TC was presented. The pre- and post-mapping simulations were conducted. The results validate the feasibility of the proposed in-system testing scheme

Keywords

built-in self test; circuit layout CAD; circuit simulation; field programmable gate arrays; integrated circuit interconnections; network routing; FPGA design tools; FPGA global interconnects; built-in self-test; design flows; field programmable gate arrays; in-system testing; interconnect routing automation; parity-based BIST scheme; post-mapping simulation; pre-mapping simulation; static timing analysis; test configurations; Built-in self-test; Circuit testing; Field programmable gate arrays; Integrated circuit interconnections; Logic arrays; Logic design; Programmable logic arrays; Routing; Switches; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2001. Canadian Conference on

Conference_Location

Toronto, Ont.

ISSN

0840-7789

Print_ISBN

0-7803-6715-4

Type

conf

DOI

10.1109/CCECE.2001.933621

Filename

933621