Run-time reconfiguration: towards reducing the density requirements of FPGAs

Author

Brunham, K. ; Kinsner, W.

Author_Institution

Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada

Volume

2

fYear

2001

fDate

2001

Firstpage

1259

Abstract

This paper presents an approach to increase the functional density of programmable logic devices (PLDs) using a programming technique called run-time reconfiguration (RTR) and the sequencing of time exclusive PLD configurations. The fundamental requirement permitting a design to increase the effective functional density of a PLD using RTR is the ability to decompose the design functionally into time exclusive stages, where each stage is synthesized as a separate PLD configuration. These distinct PLD configurations are then sequenced optimally through the device during the run-time. The distinctive feature of this approach is an increase in the effective functional density of a PLD as compared to a single-configured implementation since the effective functional density in such an RTR system is proportional to the sum of all distinct PLD configurations

Keywords

field programmable gate arrays; logic programming; FPGA; density requirements reduction; functional density; programmable logic devices; programming technique; run-time reconfiguration; single-configured implementation; time exclusive PLD configurations sequencing; Artificial neural networks; Central Processing Unit; Computer architecture; Field programmable gate arrays; Functional programming; Logic devices; Logic programming; Programmable logic arrays; Programmable logic devices; Runtime;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2001. Canadian Conference on

Conference_Location

Toronto, Ont.

ISSN

0840-7789

Print_ISBN

0-7803-6715-4

Type

conf

DOI

10.1109/CCECE.2001.933623

Filename

933623