Design of high-speed and flexible controllers in programmable logic devices

Programmable logic devices, PLDs, continue to increase in terms of logic capacity and speed. Although logic capacity is less of an issue given the large devices on the market today, designers are still challenged with meeting timing and flexibility requirements for demanding applications. We demonstrate with an example, cache coherence controllers in the NUMAchine multiprocessor, an approach that can be used to implement a design with a demanding set of requirements using PLD technology. The approach consists of two parts. First, the circuits are functionally decomposed into simpler sub-circuits. The functional decomposition improves timing performance by reducing the number of functions with large fan-in and improves flexibility by confining changes to a particular sub-circuit. Second, the CAD tools are guided in selecting devices and allocating resources. In the implementation, multiple devices were experimented with before the speed requirements were met. The resources were then allocated to increase the probability of accommodating future changes