• DocumentCode
    3238737
  • Title

    A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits

  • Author

    Ali, Sawal ; Wilcock, Reuben ; Wilson, Peter ; Brown, Andrew

  • Author_Institution
    Sch. of Electron. & Comput. Sci., Southampton Univ., Southampton
  • fYear
    2008
  • fDate
    10-14 March 2008
  • Firstpage
    152
  • Lastpage
    157
  • Abstract
    A new algorithm is presented that combines performance and variation objectives in a behavioural model for a given analogue circuit topology and process. The tradeoffs between performance and yield are analysed using a combination of a multi-objective evolutionary algorithm and Monte Carlo simulation. The results indicate a significant improvement in overall simulation time and efficiency compared to conventional simulation based approaches, without a corresponding drop in accuracy. This approach is particularly useful in the hierarchical design of large and complex circuits where computational overheads are often prohibitive. The behavioural model has been developed in Verilog-A and tested extensively with practical designs using the Spectretrade simulator. A benchmark OTA circuit was used to demonstrate the proposed algorithm and the behaviour has been verified with transistor level simulations of this circuit and a higher level filter design. This has demonstrated that an accurate performance and yield prediction can be achieved using this model, in a fraction of the time of conventional simulation based methods.
  • Keywords
    Monte Carlo methods; analogue integrated circuits; evolutionary computation; hardware description languages; integrated circuit design; integrated circuit yield; network topology; operational amplifiers; Monte Carlo simulation; OTA circuit; Verilog-A simulation; analogue circuit topology; analogue integrated circuit behavioural models; circuit yield; higher level filter design; multiobjective evolutionary algorithm; transistor level simulations; Algorithm design and analysis; Analog integrated circuits; Circuit simulation; Circuit topology; Computational modeling; Evolutionary computation; Integrated circuit modeling; Integrated circuit yield; Performance analysis; Predictive models;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe, 2008. DATE '08
  • Conference_Location
    Munich
  • Print_ISBN
    978-3-9810801-3-1
  • Electronic_ISBN
    978-3-9810801-4-8
  • Type

    conf

  • DOI
    10.1109/DATE.2008.4484678
  • Filename
    4484678