DocumentCode
3238916
Title
Performance Analysis of SoC Architectures Based on Latency-Rate Servers
Author
Vink, Jelte Peter ; Van Berkel, Kees ; Van der Wolf, Pieter
Author_Institution
Eindhoven Univ. of Technol., Eindhoven
fYear
2008
fDate
10-14 March 2008
Firstpage
200
Lastpage
205
Abstract
This paper presents a method for static performance analysis of SoC architectures. The method is based on a network calculus theory known as LR servers. This network calculus is extended and applied to make it support SoC performance analysis. Performance requirements of subsystems are elegantly captured as traffic flows and associated latency constraints. The SoC infrastructure is modeled as a set of LR servers to validate that the worst-case delays in handling the traffic flows meet the latency constraints. A multi-channel DVB-T set-top box case study demonstrates the power of the method. Key architecture choices, such as schedule or interconnect variant, can be varied easily to support exploration of architecture options.
Keywords
calculus of communicating systems; digital video broadcasting; performance evaluation; system-on-chip; DVB-T set-top box; digital video broadcasting; latency-rate servers; network calculus; static performance analysis; system-on-chip; traffic flows; worst-case delays; Calculus; Delay; Digital video broadcasting; Heart; Network servers; Performance analysis; Power system interconnection; Telecommunication traffic; Traffic control; Upper bound;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 2008. DATE '08
Conference_Location
Munich
Print_ISBN
978-3-9810801-3-1
Electronic_ISBN
978-3-9810801-4-8
Type
conf
DOI
10.1109/DATE.2008.4484686
Filename
4484686
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