Cleaning and polishing as key steps for Smart-cut(R) SOI process

Silicon on insulator technologies appear to be suitable for low power and low voltage electronics. SIMOX wafers have been considered as the best candidates to realize ULSI devices. An alternative route has been proposed by M. Bruel (1995-96) referred to as the Smart-cut process. This new process is versatile enough to fabricate SOI structures (Unibond wafers) with tuned silicon and oxide layer thicknesses. Good thickness homogeneity, low defect density, high surface quality and good electrical properties are now available in these SOI wafers. The authors show that most of these parameters depend, to some degree, on the cleaning step before wafer bonding or on the final chemical mechanical polishing process. As an example, surface roughness and defect densities are investigated by comparison with SIMOX wafer results