DocumentCode
3239119
Title
Periodic Steady-State Analysis Augmented with Design Equality Constraints
Author
Vytyaz, Igor ; Hanumolu, Pavan Kumar ; Moon, Un-Ku ; Mayaram, Kartikeya
Author_Institution
Oregon State Univ., Corvallis, OR
fYear
2008
fDate
10-14 March 2008
Firstpage
312
Lastpage
317
Abstract
A design-oriented periodic steady-state analysis is presented in this paper. The new analysis finds the values of circuit parameters that result in a desired circuit performance specified by a set of equality constraints. This is done by including the design equality constraints and the circuit parameters directly in the steady-state analysis as additional equations and unknowns. A time-domain finite difference method and the numerical implementation for the proposed analysis are described. Several examples demonstrate that the new analysis accurately and efficiently tunes circuit parameters that conform to a wide range of design specifications.
Keywords
circuit analysis computing; finite difference time-domain analysis; circuit parameters; design equality constraints; periodic steady-state analysis; time-domain finite difference method; Circuit analysis; Circuit optimization; Circuit simulation; Circuit topology; Equations; Finite difference methods; Performance analysis; Steady-state; Time domain analysis; Tuned circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 2008. DATE '08
Conference_Location
Munich
Print_ISBN
978-3-9810801-3-1
Electronic_ISBN
978-3-9810801-4-8
Type
conf
DOI
10.1109/DATE.2008.4484698
Filename
4484698
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