Processor array design for deep packet classification

We present several efficient systolic array architectures for string search for deep packet classification by using a procedural approach. We express the string search problem as a regular iterative algorithm. We also present a dependency graph from the iterative algorithm. From this dependency graph, we explore several systolic arrays for the string search algorithm. This methodology gives us the ability to pipeline some variables and broadcast other variables. This allows optimizing the architecture for speed, area and other design requirements. The proposed designs exhibit optimum speed and area complexities.