Efficient modeling and implementation of advanced encryption standard using SystemC

This paper presents a SystemC based high-level design methodology for the hardware design and implementation of the Rijndael Advanced Encryption Standard (AES) as a soft Intellectual Property (IP) core suitable for both FPGAs and ASICs. The Rijndael algorithm has been implemented with minimal design effort, to achieve low resource/area usage with optimal latency and throughput. By adopting the SystemC approach, we achieved an efficient implementation not only in terms of area, throughput and latency, but also an unified flow with a single language and reduced specification-to-gates design cycle time. The AES IP core has been modeled in SystemC and synthesized for both 0.18 μm TSMC CMOS standard cell library and Xilinx Virtex-II XC2V4000BF957-4 FPGA. Implementation results show that AES IP core which can operate in both feedback as well as nonfeedback cipher modes of operation has an area equivalent to 44,232 gates with a maximum throughput of 2.5 Gbps for ASIC and 1760 slices, 10 block SelectRAMs with a maximum throughput of 989 Mbps for Xilinx FPGA.