Image compression algorithms using re-configurable logic

The implementation of the 2D discrete cosine transform (DCT) using the Xilinx XC620D re-configurable FPGA technology, is presented. The design demonstrates that high quality circuit implementation is possible through the use of suitable data organisation (distributed arithmetic) and algorithm-to-architecture mappings (parallelism and pipelining). A throughput rate of 1.536/spl times/10/sup 7/ pixels per second for the 2D DCT circuit is achievable (equivalent to processing colour images of VGA resolution (640/spl times/480 pixels) at 25 fps) which is the equivalent of 2 million operations per second. This demonstrates that the XC6254 can produce an order of magnitude speed-up over current microprocessors.