A robust lateral power MOSFET buffered H-bridge motor driver power IC

A TTL compatible monolithic buffered H-bridge motor driver power IC implemented using low voltage power CMOS and capable of operating from 3.8 to 13.2 V is demonstrated experimentally for the first time. The buffered H-bridge is designed using an isolated lateral LDD-MOSFET structure in 2 μm BCD technology. The transient failure mechanisms of the isolated lateral MOSFET in the H-bridge topology is contrasted to the non-isolated structure through experiments and device simulations. Experiments with inductive loads indicated that the operating voltage of the non-isolated MOSFET is limited to 9 V by the snap-back of the lateral parasitic NPN. It is shown in this paper, that the transient failure mode can be eliminated and the absolute maximum voltage increased to 15 V by using an isolated lateral MOSFET structure