Validation of saturation velocity lowering in inversion layer of MOSFET´s

The accuracy of TCAD is required to ensure the predictability of the statistical simulation. The drain saturation current of short-channel MOSFETs is determined by the saturation velocity v_sat in the inversion layer, so that the modeling of v_sat is very important. In this article, v_sat in the inversion layer has been examined. We propose new parameter values far v_sat model for verification, we compare the experiments of In-Vn characteristics of 0.35 μm CMOS with the simulations using the energy transport model (ETM)