Design of a multilevel DRAM with adjustable cell capacity

A multilevel DRAM (MLDRAM) increases the per-cell storage capacity over conventional DRAM by using more than two cell signal levels. The key challenge when designing an MLDRAM is to ensure reliable operation using the more closely spaced signal levels despite the presence of on-chip noise and the inevitable small variations in circuit parameters that occur in integrated circuit (IC) production. This paper describes a test chip that implements an inherently balanced and robust MLDRAM scheme proposed by Birk et al. (see 1999 IEEE Int. Workshop on Memory Tech., Design and Testing, San Jose, CA, USA, p.102-109.). The chip has an adjustable cell capacity that can be selected from among 1, 1.5, 2 and 2.5 bits per cell. Fractional bits arise when groups of two or more cells are considered together. Thus if each cell in a pair stores one of six possible levels, then each cell has a capacity of 2.5 bits. The test chip should facilitate the experimental characterization of the proposed MLDRAM scheme