• DocumentCode
    3240087
  • Title

    Gilgamesh: A Multithreaded Processor-In-Memory Architecture for Petaflops Computing

  • Author

    Sterling, Thomas L. ; Zima, Hans P.

  • Author_Institution
    California Institute of Technology
  • fYear
    2002
  • fDate
    16-22 Nov. 2002
  • Firstpage
    48
  • Lastpage
    48
  • Abstract
    Processor-in-Memory (PIM) architectures avoid the von Neumann bottleneck in conventional machines by integrating high-density DRAM and CMOS logic on the same chip. Parallel systems based on this new technology are expected to provide higher scalability, adaptability, robustness, fault tolerance and lower power consumption than current MPPs or commodity clusters. In this paper we describe the design of Gilgamesh a PIM-based massively parallel architecture, and elements of its execution model. Gilgamesh extends existing PIM capabilities by incorporating advanced mechanisms for virtualizing tasks and data and providing adaptive resource management for load balancing and latency tolerance. The Gilgamesh execution model is based on macroservers a middleware layer which supports object-based runtime management of data and threads allowing explicit and dynamic control of locality and load balancing. The paper concludes with a discussion of related research activities and an outlook to future work.
  • Keywords
    Petaflops computing; Processor-In-Memory; data; irregular applications; parallel architectures; CMOS logic circuits; CMOS process; CMOS technology; Computer architecture; Energy consumption; Fault tolerant systems; Load management; Parallel architectures; Robustness; Scalability; Petaflops computing; Processor-In-Memory; data; irregular applications; parallel architectures;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Supercomputing, ACM/IEEE 2002 Conference
  • ISSN
    1063-9535
  • Print_ISBN
    0-7695-1524-X
  • Type

    conf

  • DOI
    10.1109/SC.2002.10061
  • Filename
    1592884