Low power digital filters based on constrained least squares solution

We investigate a top-down design strategy for reducing the number of operations in digital filters based on a constrained least squares (CLS) solution. The proposed strategy reduces the switching activity in the VLSI implementation of such filters by constraining the Hamming weight (HW) of coefficients, thereby, restricting the number of power consuming operations required to compute the output. The power constrained least squares (PCLS) coefficients obtained from the original coefficients can be used in conjunction with appropriately modified multipliers to reduce the power consumption. We also show that for filters designed using the least squares (LS) method, the solution obtained using the proposed method is an optimal solution to the operations constrained by the LS problem. Finally, we extend this approach to adaptive filters based on the LS method.