Design Method and New Architecture of Sub-Harmonic Balanced Cold FET Mixer for MVDS Applications

This paper reports a novel MMIC balanced sub-harmonic cold FET mixer for MVDS applications using 0.15 mum GaAs pHEMT. The mixer, which includes a LO buffer amplifier, was optimized for highly linear up-conversion performance in the 40.5-43.5 GHz RF band, 19.5-20.5 GHz LO band and 2.45-3.45 GHz IF band. A dedicated simulation method has been developed to optimize conversion loss and determine optimum matching. To achieve better (2LO-to-RF) isolation a specific balanced architecture for sub-harmonic mixing has been elaborated. This leads to simulation results of 13 plusmn 0.5dB conversion losses associated to high IF input power at 1dB compression of 17dBm, and (2LO-to-RF) isolation of 40dB