Implementation of DSP-RAM: an architecture for parallel digital signal processing in memory

We describe a synthesizable implementation in VHDL of a parallel architecture for signal processing called DSP-RAM. DSP-RAM is an enhanced version of the earlier computational RAM (C-RAM) architecture proposed by Elliott (see Ph.D. thesis, Dept.of Electrical Engineering, University of Toronto, Canada, 1998). Like C-RAM, the new architecture integrates on the same chip both memory storage and single instruction stream, multiple data stream parallel data processing. Unlike in C-RAM, each processing element contains a multiplier-accumulator that can directly handle 16-bit data words; in contrast, C-RAM is organized to perform massively-parallel, bit-serial computation. The VHDL DSP-RAM model was verified by simulating three promising applications: FIR digital filtering, the discrete cosine transform (DCT), and vector quantization (VQ). A controller circuit along with a simple micro-programming language were also designed to facilitate the implementation of applications