A scalable low-power digital communication network architecture and an automated design path for controlling the analog/RF part of SDR transceivers

Emerging new wireless standards, the move towards multi-standard transceivers, and ultimately software- defined radios imposes the need for a tighter interaction between digital baseband and analog/RF parts. Software- defined radio transceivers may face more than 400 control bits in the analog/RF part. Configuring of the transmit/receive chain to particular standards, monitoring of front-end performance, and dynamic control of front-end behavior requires a tight bidirectional interaction. We have developed a generic concept of a flexible and scalable low-power digital communication network in a multi-standard analog/RF front-end. Our approach is layout-friendly, reduces interconnect area significantly (by 96%) compared to a star topology, scales easily with analog/RF design changes such as pin additions, and exhibits a generic bidirectional interface to the system and digital designer. Moreover, an almost fully automated design flow - starting from an on-chip connection list for all analog blocks up to VHDL code generation - has been developed and implemented, reducing design effort and potential errors. The architecture and the design flow have been successfully proven in two 0.13-um full software-defined radio transceiver designs. In the first design, the flow was still manually instantiated. In the second design, the automated flow was used and led to a significant design- time speed-up.