• DocumentCode
    3240343
  • Title

    Novel circuit styles for minimization of floating body effects in scaled PD-SOI CMOS

  • Author

    Das, Koushik K. ; Brown, Richard B.

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
  • fYear
    2003
  • fDate
    20-21 Feb. 2003
  • Firstpage
    29
  • Lastpage
    34
  • Abstract
    SOI (silicon-on-insulator) technology suffers from a number of floating body effects, most notably parasitic bipolar and history effects. These are influenced by the rapidly increasing gate tunneling current caused by an ultra-thin gate oxide, even at scaled VDDs. This paper analyzes these effects in detail and proposes a number of novel circuit styles to minimize them. Simulation results are based on model parameters from an AMD 0.25 μm PD-SOI process.
  • Keywords
    CMOS integrated circuits; silicon-on-insulator; tunnelling; 0.25 micron; floating body effect; gate tunneling current; history effect; parasitic bipolar effect; partially depleted SOI CMOS circuit; ultra-thin gate oxide; Circuits; Diodes; Fault location; History; Impact ionization; Minimization; Silicon on insulator technology; Tunneling; Very large scale integration; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on
  • Print_ISBN
    0-7695-1904-0
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2003.1183350
  • Filename
    1183350
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3240343