A novel architecture for VLSI implementation of the 2-D DCT/IDCT

Author

Cucchi, S. ; Fratti, M.

Author_Institution

DSP Lab., ALCATEL Telettra, Vimercate, Italy

Volume

5

fYear

1992

fDate

23-26 Mar 1992

Firstpage

693

Abstract

The implementation of a 8×8 two-dimensional forward/inverse discrete cosine transform (DCT) chip is presented. The structure is highly regular and modular and the DCT computation is carried out using registers and adders only. A fully pipelined structure based on a new approach for serial arithmetic computation allows a high throughput capability (i.e., up to 40 MHz). The chip is fully functional and is being employed in the Alcatel Telettra HDTV (high definition television) codec. Fabricated in 1ηm double-metal CMOS technology by LSI Logic, the chip uses approximately 57000 transistors which occupy a 218-pad die area of 8.6 mm×8.6 mm (56 pads are used)

Keywords

CMOS integrated circuits; VLSI; codecs; discrete cosine transforms; high definition television; pipeline processing; Alcatel Telettra HDTV; LSI Logic; adders; codec; die area; double-metal CMOS technology; pipelined structure; registers; serial arithmetic computation; throughput capability; two-dimensional forward/inverse discrete cosine transform; Arithmetic; CMOS technology; Codecs; Computer architecture; Discrete cosine transforms; HDTV; Registers; TV; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1992. ICASSP-92., 1992 IEEE International Conference on

Conference_Location

San Francisco, CA

ISSN

1520-6149

Print_ISBN

0-7803-0532-9

Type

conf

DOI

10.1109/ICASSP.1992.226501

Filename

226501