Digital implementation of a neural network

Summary form only given. The major problem regarding hardware implementation of neural networks is due to the fact that the number of interconnections grow quadratically with the number of pressing elements in each layer. The hard-limiting neuron model, well suited for digital technology, provides a base for implementing neural networks in hardware designs. A neural-processing chip is developed using this concept. It links neurons along a serial shift register, eliminating the need for an enormous array of interconnecting wires. The neurons process information in parallel while communicating data serially. Connection weights are stored locally with each neuron, relieving the burden on the network structure to maintain weighted connections. Each chip has 16 neurons and a memory holding a 16*128 array for weight. Up to 8 chips can be connected in tandem, increasing the size of the system to a maximum of 128 neurons. Due to the versatile design of the neural-processing chip, it provides a vehicle for researchers to emulate or implement various neural network architectures.<>