The architecture of a vector digital signal processor for video coding

Develops a high-performance vector digital signal processor (VDSP) for video coding that can execute instructions at 60 MHz. The VDSP employs a vector pipeline (VP) architecture, which is very well suited for image processing. In the VDSP, a DCT/IDCT circuit (CCITT standard), a two-dimensional space address generator (SAG), and an enhanced ALU to the VP architecture are included, and, as a result, a performance of 2.0 GOPS (giga operation per second) was achieved. The encoder and the decoder specified in CCITT H.261 (Full-CIF mode at 15 frame/s, 64 kb/s) can be realized with two VDSP chips, and one VDSP chip, respectively