The architecture of a vector digital signal processor for video coding

Author

Araki, Toshiyuki ; Toyokura, Masaki ; Wakamori, Masahiro ; Aono, Kunitoshi

Author_Institution

Matsushita Electric Ind. Co. Ltd., Osaka, Japan

Volume

5

fYear

1992

fDate

23-26 Mar 1992

Firstpage

681

Abstract

Develops a high-performance vector digital signal processor (VDSP) for video coding that can execute instructions at 60 MHz. The VDSP employs a vector pipeline (VP) architecture, which is very well suited for image processing. In the VDSP, a DCT/IDCT circuit (CCITT standard), a two-dimensional space address generator (SAG), and an enhanced ALU to the VP architecture are included, and, as a result, a performance of 2.0 GOPS (giga operation per second) was achieved. The encoder and the decoder specified in CCITT H.261 (Full-CIF mode at 15 frame/s, 64 kb/s) can be realized with two VDSP chips, and one VDSP chip, respectively

Keywords

digital signal processing chips; parallel architectures; pipeline processing; 60 MHz; CCITT H.261; VDSP chips; decoder; encoder; image processing; two-dimensional space address generator; vector digital signal processor; vector pipeline; video coding; Bismuth; Circuits; Communication industry; Decoding; Digital signal processors; Image processing; Image storage; Pipelines; Toy industry; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1992. ICASSP-92., 1992 IEEE International Conference on

Conference_Location

San Francisco, CA

ISSN

1520-6149

Print_ISBN

0-7803-0532-9

Type

conf

DOI

10.1109/ICASSP.1992.226504

Filename

226504