The VLSI design and implementation of the array processors of a multilayer vision system architecture

Author

Saha, B. ; Mertoguno, J.S. ; Bourbakis, N.G.

Author_Institution

Dept. of Electr. Eng., Binghamton Univ., NY, USA

fYear

1995

fDate

24-26 Jul 1995

Firstpage

125

Lastpage

128

Abstract

This paper describes the VLSI design and simulation of the lower layer processors of the KYDON vision system. KYDON is a completely autonomous, hierarchical, multilayered image understanding system. The VLSI design of the individual components as well as the timing simulation results of the processor array have been presented. The system runs at 50 MHz and promises a high processing rate of 300 image frames/sec

Keywords

VLSI; computer vision; digital simulation; parallel processing; KYDON vision system; VLSI design; array processors; multilayer vision system architecture; multilayered image understanding system; timing simulation; Computational modeling; Computer vision; Coprocessors; Image recognition; Machine vision; Nonhomogeneous media; Pattern recognition; Systolic arrays; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Application Specific Array Processors, 1995. Proceedings. International Conference on

Conference_Location

Strasbourg

ISSN

1063-6862

Print_ISBN

0-8186-7109-2

Type

conf

DOI

10.1109/ASAP.1995.522913

Filename

522913

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3240700