Title :
Interfacing synchronous DRAMs to Pentium processors
Abstract :
The steady increase in the bus frequencies of microprocessors necessitates the use of new memory technologies in order to keep up with these frequencies. Synchronous memory technologies in general, and Synchronous DRAMs in particular, offer advantages for these designs as they provide the required frequencies as well as a clean memory interface design due to their synchronous nature. We will discuss the design of a system based on the Intel Pentium microprocessor and SDRAMs. The memory interface between the Pentium and the SDRAMs is implemented using Gate Array Logic (GAL) devices
Keywords :
Clocks; Frequency; Logic arrays; Logic devices; Microprocessors; Pins; Random access memory; Read-write memory; SDRAM; Signal processing;
Conference_Titel :
WESCON/'95. Conference record. 'Microelectronics Communications Technology Producing Quality Products Mobile and Portable Power Emerging Technologies'
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2636-9
DOI :
10.1109/WESCON.1995.485246
