Quantitative Productivity Measurement in IC Design

This paper describes ongoing research in the field of quantitative productivity measurement in IC Design and simulation of different scenarios as decision support. Five topics out of this research field allow an insight in the preparation of real design flows for productivity measurement and how these measurements are used for analysis, simulation and optimization of design flows. This paper starts with an introduction in section 1 of the PRODUKTIV+ project in which most of the research has been done. The modeling of projects and extraction of the important indicators complexity and quality is explained in sections 2 and 3. In section 4 Synopsys as an EDA vendor from outside of PRODUKTIV+ adds its view on productivity measurement. Section 5 contributes to the modeling of a verification process for productivity simulations. Section 6 explains an optimization process for a microprocessor design flow under productivity considerations. Most of this work has been carried out in the PRODUKTIV+ project (label 01 M 3077) that is partly funded by the German government.