Fault modeling and verification of multi-million transistor VLSI circuits

Ultra-high speed VLSI chips require high-density custom design. This paper describes a tool that extracts fault models/logic models from schematics of multi-million transistor chips. AUTOMOD is used to generate fault models for custom designed circuits. This tool is also found extremely valuable in capturing design error, such as a wrong connection of physical nets, missing pins and wrong implementations. It can also be used as a verification tool for physical and logical checking