An investigation of clock-race conditions in NORA dynamic CMOS circuits

Author

Puree, Gaurav ; Punia, Virender ; Yuan, Fei

Author_Institution

Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, Ont., Canada

Volume

1

fYear

2001

fDate

2001

Firstpage

595

Abstract

This paper investigates the clock-race condition of NORA pipelined logic circuits. It is shown that by specifying positive and negative clock skews, both n-p and p-n NORA pipelined logic circuits are sensitive to clock skews. These findings differ from those presented in the original paper [1]. To verify these observations, a NORA-based D-latch and two full adders are implemented using a 0.35 micron CMOS technology and are simulated using Spectre with the presence of both the positive and negative clock skews. The simulation results are presented

Keywords

CMOS logic circuits; SPICE; adders; circuit simulation; clocks; digital simulation; flip-flops; hazards and race conditions; pipeline processing; 0.35 mum; CMOS technology; NORA dynamic CMOS circuits; NORA-based D-latch; SPICE simulation; Spectre; clock-race conditions; full adders; high-speed CMOS digital circuits; n-p NORA pipelined logic circuits; negative clock skew; p-n NORA pipelined logic circuit; positive clock skew; simulation results; Adders; CMOS logic circuits; CMOS technology; Circuit simulation; Clocks; Inverters; Latches; Logic circuits; Logic functions; MOSFETs;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2001. Canadian Conference on

Conference_Location

Toronto, Ont.

ISSN

0840-7789

Print_ISBN

0-7803-6715-4

Type

conf

DOI

10.1109/CCECE.2001.933751

Filename

933751