Title :
A throughput/complexity analysis for the VLSI implementation of LDPC decoder
Author :
Fanucci, Luca ; Ross, Francesco
Author_Institution :
IEIIT Nat. Res. Council, Pisa, Italy
Abstract :
This paper presents an analysis of the VLSI complexity of different LDPC decoder implementations. Both fully parallel and serial solutions are considered and compared in terms of architectural issues, hardware complexity, power consumption and supported throughput. To provide numeric results a 1/2 rate, (3,6) regular LDPC code with a 2048 codeword has been considered and area complexity estimations have been carried out with reference to a 0.18 μm standard-cell CMOS technology.
Keywords :
CMOS logic circuits; VLSI; iterative decoding; parity check codes; wireless LAN; 0.18 micron; 2048 codeword; LDPC decoder implementation; VLSI; WLAN; linear density parity check code; parallel solution; power consumption; serial solution; standard-cell CMOS technology; very large scale integration; wireless local area network; Channel coding; Energy consumption; Equations; Hardware; Iterative decoding; Message passing; Parity check codes; Sparse matrices; Throughput; Very large scale integration;
Conference_Titel :
Signal Processing and Information Technology, 2004. Proceedings of the Fourth IEEE International Symposium on
Print_ISBN :
0-7803-8689-2
DOI :
10.1109/ISSPIT.2004.1433805
