Design of a multiprocessor DSP chip for flexible information processing

Author

Chang, Chia-Fen ; Sheu, Bang J. ; Okada, Hiroto

Author_Institution

Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA

Volume

5

fYear

1992

fDate

23-26 Mar 1992

Firstpage

637

Abstract

Architecture and custom circuit design of a multiprocessor chip for digital signal processing (DSP) and digital image processing have been developed. Mappings of digital image processing and neural network algorithms are presented. The processor design supports the execution of key signal processing functions. The processing elements can be connected in a 1D linear ring or 2D systolic mesh array. A microprogrammed controller is used to enhance the processor performance. Each processor occupies 4.1 mm² by using an industrial-scale 0.5-μm CMOS technology from TRW Inc. Sixty-four processing elements can be implemented in a 1.5-cm×1.8-cm chip and achieve 2.56 billion calculations per second

Keywords

CMOS integrated circuits; VLSI; application specific integrated circuits; digital signal processing chips; microcontrollers; neural chips; systolic arrays; 0.5 micron; 1.5 cm; 1.8 cm; 1D linear ring; 2D systolic mesh array; CMOS technology; VLSI; architecture; custom circuit design; digital image processing; digital signal processing; flexible information processing; microprogrammed controller; multiprocessor DSP chip; neural network algorithms; Array signal processing; CMOS process; CMOS technology; Circuit synthesis; Digital images; Digital signal processing chips; Neural networks; Process design; Signal design; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1992. ICASSP-92., 1992 IEEE International Conference on

Conference_Location

San Francisco, CA

ISSN

1520-6149

Print_ISBN

0-7803-0532-9

Type

conf

DOI

10.1109/ICASSP.1992.226540

Filename

226540