Power Managed Packet Switching

High power dissipation in packet switches and routers is fast turning into a key problem, owing to increasing line speeds and decreasing chip sizes. To address this issue, we introduce and develop the notion of a power-managed input-queued (PMIQ) switch in this paper. A PMIQ switch is an input-queued switch with an additional hierarchy of control to regulate the power dissipated by the switch. We formulate the joint scheduling and power management problem for a PMIQ switch as a dynamic program (DP). Leveraging intuition gained from provable structural properties of the optimal solution to the DP, we propose the power-aware switch scheduling (PASS) switch management policy. PASS dynamically selects the rate/speed at which the switch operates, in conjunction with the switch configuration, as a function of the backlogs of the input buffers. PASS can easily be tuned to tradeoff high power consumption for larger queuing delays. Experimental results show that PASS yields an attractive power-delay tradeoff relative to the benchmark maximum weight matching (MWM) scheduler. The low computational complexity of PASS makes it amenable to implementation in large, high-speed switches.