Title :
Task scheduling in the Georgia Tech digital signal multiprocessor
Author :
Curtis, Bryce A. ; Madisetti, Vijay K.
Author_Institution :
IBM, Boca Raton, FL, USA
Abstract :
The use of realistic structural and behavioral level descriptions of digital signal multiprocessors to find rate optimal and processor optimal schedules for implementation on multiprocessor digital signal processor (DSP) systems is addressed. Unlike previous work, the digital signal multiprocessor compiler (DSMP-C1) explicitly considers the location of operands, the number of accumulators and registers, the size of on-chip and external memories, the size of communication buffers, and inter-processor communications. The algorithm implicitly retimes and pipelines the flow graph and generates overlapping PSSIMD schedules that are both rate and processor optimal. When compared to previously published scheduling algorithms, the DSMP-C1 algorithm produces significantly shorter iteration periods
Keywords :
digital signal processing chips; multiprocessing programs; pipeline processing; program compilers; scheduling; DSMP-C1; Georgia Tech digital signal multiprocessor; PSSIMD schedules; accumulators; architecture; communication buffers; digital signal multiprocessor compiler; external memory size; inter-processor communications; on-chip memory size; pipelining; registers; task scheduling; Digital signal processing; Digital signal processors; Flow graphs; Optimal scheduling; Pipelines; Processor scheduling; Registers; Scheduling algorithm; Signal processing; Signal processing algorithms;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1992. ICASSP-92., 1992 IEEE International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-0532-9
DOI :
10.1109/ICASSP.1992.226551
