Title :
On the FPGA board level routing problem
Author :
Song, Xiaoyu ; Wang, Yuke
Author_Institution :
Dept. IRO, Montreal Univ., Que., Canada
Abstract :
We study a two-terminal board level routing problem applicable to FPGA-based logic emulation systems. The problem was studied by W. Mak and D.F. Wong (see IEEE Trans. CAD, vol.16, no.3, 1997), where an algorithm of O(n2) time was proposed, where n is the number of nets. We present a new and simple O(n)-time routing algorithm for solving the problem. A new precise I/O capacity constraint for routability is given by taking other criteria (e.g., the number of chips) into consideration
Keywords :
field programmable gate arrays; logic CAD; network routing; FPGA-based logic emulation; I/O capacity constraint; O(n)-time routing algorithm; two-terminal board level routing problem; Application specific integrated circuits; Emulation; Field programmable gate arrays; Integrated circuit interconnections; Iterative algorithms; Logic design; Logic devices; Logic programming; Programmable logic arrays; Routing;
Conference_Titel :
Electrical and Computer Engineering, 1998. IEEE Canadian Conference on
Conference_Location :
Waterloo, Ont.
Print_ISBN :
0-7803-4314-X
DOI :
10.1109/CCECE.1998.682778
