Conditional Partial Order Graphs and Dynamically Reconfigurable Control Synthesis

The paper introduces a new formal model for specifying control paths in the context of asynchronous system design. The model, called conditional partial order graph (CPOG), is capable of capturing concurrency and choice in a system´s behaviour in a compact and efficient way. A problem of CPOG synthesis is formulated and solved; various CPOG optimisation techniques are presented. The introduced model can be used for the specification of system behaviour and for synthesis of area-efficient dynamically reconfigurable controllers. The synthesis of a controller is based on a novel generic architecture, called transition sequence encoder (TSE). The synthesized controllers are speed independent and thus very robust to parametric variations. The ideas presented in the paper can be applied for CPU control synthesis as well as for synthesis of different kinds of event-coordination circuits often used in data coding and communication in digital systems.