DocumentCode
3241711
Title
SDS: a framework for the design of DSP ASICs
Author
Bayoumi, M.A. ; Ramakrishna, N.A. ; Israni, V. ; Jayam, R.K.
Author_Institution
Univ. of Southwestern Louisiana, Lafayette, LA, USA
Volume
5
fYear
1992
fDate
23-26 Mar 1992
Firstpage
545
Abstract
A brief overview is given of the Sphinx Design System (SDS), a high-level synthesis system consisting of an integrated and interacting set of tools for the synthesis of digital circuits. The system is specifically tuned to the synthesis of digital signal processor (DSP) application specific integrated circuits (ASICs) from behavioral specifications written in Verilog. SDS consists of tools for behavioral, structural and logical synthesis, technology mapping and for simulation. C and SKILL have been used as the implementation and extension languages and the system will be integrated into the Cadence Edge Framework. SPS, the scheduling and allocation subsystem of SDS, is discussed in some detail
Keywords
application specific integrated circuits; circuit CAD; digital signal processing chips; C; Cadence Edge Framework; SKILL; Sphinx Design System; Verilog; allocation subsystem; application specific integrated circuits; behavioral specifications; behavioral synthesis; digital circuits; digital signal processor; high-level synthesis system; logical synthesis; scheduling; simulation; structural synthesis; technology mapping; Application specific integrated circuits; Circuit simulation; Digital circuits; Digital signal processing; Digital signal processors; Hardware design languages; High level synthesis; Integrated circuit synthesis; Integrated circuit technology; Signal synthesis;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, 1992. ICASSP-92., 1992 IEEE International Conference on
Conference_Location
San Francisco, CA
ISSN
1520-6149
Print_ISBN
0-7803-0532-9
Type
conf
DOI
10.1109/ICASSP.1992.226562
Filename
226562
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