DC integration level analysis of low-Vdd CMOS circuit using worst-case noise margin map

DC integration level of low-Vdd CMOS circuit is analyzed using the worst-case noise margin map with the consideration of MOSFET Vth deviation (σVth). In the case of the ultra-low power CMOS of which Vdd is as low as 0.5 V, the analysis shows that the DC integration level strongly depends on σVth, although CMOS circuit has large operating area. It varies from one gate to 10 G gates when σVth changes from 24 mV to 14 mV. This means, in the future Low-Vdd era, the integration level of CMOS LSI is determined not only by the total LSI power dissipation but also by σVth