DC integration level analysis of low-Vdd CMOS circuit using worst-case noise margin map

Author

Kameyama, A. ; Ohta, M. ; Fuse, T. ; Ohuchi, K.

Author_Institution

Toshiba R&D Center, Kawasaki, Japan

fYear

2001

fDate

2001

Firstpage

58

Lastpage

59

Abstract

DC integration level of low-Vdd CMOS circuit is analyzed using the worst-case noise margin map with the consideration of MOSFET Vth deviation (σVth). In the case of the ultra-low power CMOS of which Vdd is as low as 0.5 V, the analysis shows that the DC integration level strongly depends on σVth, although CMOS circuit has large operating area. It varies from one gate to 10 G gates when σVth changes from 24 mV to 14 mV. This means, in the future Low-Vdd era, the integration level of CMOS LSI is determined not only by the total LSI power dissipation but also by σVth

Keywords

CMOS integrated circuits; integrated circuit modelling; integrated circuit noise; large scale integration; low-power electronics; 0.5 V; DC integration level analysis; LSI power dissipation; MOSFET Vth deviation; integration level; low-Vdd CMOS circuit; operating area; ultra-low power CMOS; worst-case noise margin map; Circuit analysis; Circuit noise; Equations; FETs; Fuses; Large scale integration; MOSFET circuits; Noise level; Research and development; Temperature distribution;

fLanguage

English

Publisher

ieee

Conference_Titel

Statistical Methodology, IEEE International Workshop on, 2001 6yh.

Conference_Location

Kyoto

Print_ISBN

0-7803-6688-3

Type

conf

DOI

10.1109/IWSTM.2001.933827

Filename

933827