System level prototyping for embedded networking applications

Faster and faster time-to-market demands necessitate a very thorough and flexible verification process of any embedded networking system design, in order to minimize the risk of costly hardware and software re-designs. With gate counts (1M+ gates), a relatively seamless design flow and quick programmability, the field-programmable gate array (FPGA) is a great tool for creating a hardware prototype test-bench that allows integration of the RTL (register transfer level) code with actual physical interfaces. This paper explores some of the FPGA design methodologies and implementations used for verifying a `residential gateway´ system-level prototyping environment