Minimizing charge-up damage during dielectric etchers hardware and process development stages

Plasma processing induced damage of thin gate oxide is a major concern for device integrity in etch or thin film module process development. Since it was concluded that plasma nonuniformity is the root cause of such charging damage (Fang and McVittie, 1992; Gabriel and McVittie, 1992), much of the emphasis has shifted to plasma processing equipment makers to deliver more uniform plasma sources. Also, device manufacturers are now asking equipment vendors to carry greater process development burdens due to the mounting pressure of ever shortening product lifetimes and the increasing cost of volume manufacturing fabs. Therefore, hardware design and process development at an equipment vendor´s lab strongly influences charging damage at the manufacturers. Recently, electron shading induced charge-up damage (Hashimoto, 1993, 1994) emerged as another key challenge, partly due to plasma´s higher electron temperatures (Hashimoto et al., 1996), and partly due to the large topography variation inherited from device design and process flows (Arnold and Sawin, 1991; Vahedi et al., 1997). In this paper, we discuss, from an equipment vendor´s point of view, studies in hardware and process development to minimize charge-up damage in dielectric etchers. The dielectric etch module is subject to both plasma nonuniformity induced damage and electron shading effects, due to the plasma sources used as well as the innate high aspect ratios of contact and via holes. Consequently, close collaboration with device makers is required