DocumentCode
3242068
Title
Designing function configuration decoders for the PAnDA architecture using multi-objective Cartesian Genetic Programming
Author
Walker, James Alfred ; Trefzer, Martin A. ; Tyrrell, Andy M.
Author_Institution
Dept. of Electron., Univ. of York, York, UK
fYear
2013
fDate
16-19 April 2013
Firstpage
96
Lastpage
103
Abstract
The Programmable Analogue and Digital Array (PAnDA) is a novel reconfigurable architecture, which allows variability aware design and rapid prototyping of digital systems. Exploiting the configuration options of the architecture allows the post-fabrication correction and optimisation of circuits directly in hardware using bio-inspired techniques. In order to reduce the overhead of extra configuration memory and area consumption, a portion of the configuration memory required to configure the logic functionality of the Configurable Analogue Blocks (CABs) in the PAnDA architecture is replaced by Function Configuration Decoders (FCDs). In the past, bio-inspired approaches based on Cartesian Genetic Programming have been demonstrated as a suitable method for designing such circuit topologies. As the area of the FCDs is a primary concern, in addition to performance, a form of CGP which utilises a multi-objective strategy (MO-CGP) is used to evolve FCD designs for the two types of CAB present in the PAnDA architecture. The results show that MO-CGP is capable of evolving and optimising FCDs that are optimal for area and performance for both CABs. A PAnDA prototype chip containing FCDs is currently being fabricated. Also, when compared with designs produced by a commercial synthesis tool, the MO-CGP designs are smaller, faster, and more power efficient.
Keywords
circuit optimisation; genetic algorithms; logic design; network topology; performance evaluation; programmable logic arrays; reconfigurable architectures; CAB; FCD designs; MO-CGP; PAnDA architecture; PAnDA prototype chip; area consumption reduction; bio-inspired techniques; circuit optimisation; circuit topologies; configurable analogue blocks; configuration memory; digital systems; extra configuration memory overhead reduction; function configuration decoder design; logic functionality configuration; multiobjective Cartesian genetic programming; multiobjective strategy; post-fabrication correction; programmable analogue and digital array; rapid prototyping; reconfigurable architecture; variability aware design; Decoding; Field programmable gate arrays; Logic gates; Optimization; Sociology; Statistics; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Evolvable Systems (ICES), 2013 IEEE International Conference on
Conference_Location
Singapore
Type
conf
DOI
10.1109/ICES.2013.6613288
Filename
6613288
Link To Document