DocumentCode :
3242115
Title :
Effect of plasma density and uniformity, electron temperature, process gas, and chamber on electron shading damage
Author :
Siu, Stanley ; Patrick, Roger ; Vahedi, Vahid ; Alba, Simone ; Valentini, Grazia ; Colombo, Paolo
Author_Institution :
Lam Res. Corp., Fremont, CA, USA
fYear :
1999
fDate :
1999
Firstpage :
25
Lastpage :
28
Abstract :
Electron shading is a major plasma process-induced device damage mechanism in high-density etching. Patrick et al (1997) showed that although gross plasma nonuniformity can cause damage, nonuniformities seen in modern commercial etchers contribute negligible damage. Vahedi et al. (1997) derived an analytic model that clarifies the contribution of plasma and device parameters to topography induced charging. Electron temperature and plasma density are the major damage parameters for plasma. Modeling and preliminary shading coefficient measurements show that plasma nonuniformity is indeed only a small contribution. Other major factors in plasma processing induced damage relate to the device, and are the gate oxide activation electric field, effective mass constant, and gate oxide thickness. Finally, topography dependent shading parameters need to be considered. These are a function of minimum line width, aspect ratio, and antenna ratio. Protection diodes and transient fuses (Krishnan et al., 1998) may help mitigate shading damage effects, but do not change the charging mechanism, namely electron shading. This work examines the role of plasma parameters on V th shifts in transistors fabricated in a flash memory process where metal 1 and/or metal 2 were etched in either a Lam TCPTM 9600SE or Lam TCPTM 9600PTX chamber. The plasma parameters varied were plasma density, electron temperature, and plasma uniformity. The role of chamber gap height in the 9600SE was examined and the results compared to the those in the 9600PTX. The role of a lighter ion in decreasing damage as suggested by Tabara (1998) was also examined
Keywords :
CMOS memory circuits; dielectric thin films; flash memories; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit yield; plasma density; plasma materials processing; plasma temperature; sputter etching; surface charging; surface topography; CMOS flash memory process; Lam TCP 9600PTX etch chamber; Lam TCP 9600SE etch chamber; antenna ratio; aspect ratio; chamber gap height; charging mechanism; device parameters; effective mass constant; electron shading; electron shading damage; electron temperature; flash memory process; gate oxide activation electric field; gate oxide thickness; high-density plasma etching; metal 1 etch; metal 2 etch; minimum line width; modeling; plasma density; plasma nonuniformity; plasma parameters; plasma process-induced device damage mechanism; plasma processing induced damage; plasma uniformity; process chamber; process gas; protection diodes; shading coefficient measurements; shading damage effects; threshold voltage shifts; topography dependent shading parameters; topography induced charging; transient fuses; Effective mass; Electrons; Etching; Plasma applications; Plasma density; Plasma devices; Plasma materials processing; Plasma measurements; Plasma temperature; Surfaces;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Plasma Process-Induced Damage, 1999 4th International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-9651577-3-3
Type :
conf
DOI :
10.1109/PPID.1999.798800
Filename :
798800
Link To Document :
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